FE Electrical Digital Systems Practice Problems

Answer: B) \(239\)

The Handbook's positional formula for a base-\(r\) number multiplies each digit by \(r\) raised to its position, counting from zero at the right:

$$357_8 = 3 \times 8^2 + 5 \times 8^1 + 7 \times 8^0 = 192 + 40 + 7 = 239$$

Octal digits run from 0 to 7, so \(357_8\) is a legal octal number, and the weights are 64, 8 and 1. A quick bound check: \(357_8\) must lie between \(300_8 = 192\) and \(400_8 = 256\), which 239 does. The Handbook's code table shows why octal is convenient in digital work: each octal digit is exactly three bits, so \(357_8 = 011\,101\,111_2\), and the same 239 comes from \(128 + 64 + 32 + 8 + 4 + 2 + 1\).

232 is \(192 + 40\), the units digit dropped; the last digit carries weight \(8^0 = 1\), not zero.

491 puts the weights on backwards, \(3 \times 1 + 5 \times 8 + 7 \times 64\); the leftmost digit carries the largest weight.

855 treats the digits as hexadecimal, \(3 \times 256 + 5 \times 16 + 7\), the wrong base.

Answer: A) \(Q = 0\) and \(\overline{Q} = 0\), so the two outputs are no longer complementary

Handbook: FE Reference Handbook 10.6, Electrical and Computer Engineering → Flip-Flops, p. 396 (PDF viewer: page 402). Its SR next-state table covers this input, but only with a label:

$$SR = 00 \rightarrow Q_n \text{ (no change)} \qquad 01 \rightarrow 0 \qquad 10 \rightarrow 1 \qquad 11 \rightarrow x \text{ (invalid)}$$

The Handbook writes invalid and stops. It never shows a latch built from gates — the word latch does not appear in it at all — so it cannot tell you what the two outputs actually do. The figure can.

Step 1 – Write the two gate equations. Read the cross-coupling straight off the drawing: each gate takes one external input and the other gate's output.

$$Q = \overline{R + \overline{Q}} \qquad\qquad \overline{Q} = \overline{S + Q}$$

Step 2 – Use the one property of a NOR that settles it. A NOR outputs 1 only when every input is 0. So a single high input pins its output low, whatever the other input is doing:

$$Q = \overline{1 + \cdots} = 0 \qquad\qquad \overline{Q} = \overline{1 + \cdots} = 0$$

Step 3 – Answer: both outputs sit at 0 — (A).

This result is stable, not undefined. Substitute \(Q = \overline{Q} = 0\) back into both equations and they hold. Start the latch in the set state or the reset state and it lands here within two gate delays either way, so the outcome does not even depend on history. What breaks is not the arithmetic but the naming: the pin labelled \(\overline{Q}\) is supposed to carry the complement of \(Q\), and here the two are equal. A latch that cannot honour its own labels is not doing its job, which is the practical reason this input is called forbidden.

The real trouble comes later. Drop \(S\) and \(R\) to 0 at the same instant and each gate now sees 0 outside and 0 fed back, so both try to go high at once, each then forcing the other down. Whichever gate is a few picoseconds faster decides where the latch lands, and the schematic cannot tell you which. That race is a separate question in its own right; what matters here is that it happens on release, not while the inputs are held.

Step 4 – Eliminate the distractors:

(B) \(Q = \overline{Q} = 1\) is the right idea applied to the wrong latch. Build the same circuit from cross-coupled NAND gates and the inputs become active-low; there the forbidden combination is \(\overline{S} = \overline{R} = 0\) and it drives both outputs high. Same broken complementarity, opposite rail. Always check which gate the latch is made of before predicting the levels.

(C) \(Q = 0\), \(\overline{Q} = 1\) is the ordinary reset, which needs \(R = 1\) with \(S = 0\). Here \(S\) is high too, so the lower gate is pinned low and \(\overline{Q}\) cannot reach 1.

(D) \(Q = 1\), \(\overline{Q} = 0\) is the ordinary set, needing \(S = 1\) with \(R = 0\). Here \(R\) is high too, so the upper gate is pinned low and \(Q\) cannot reach 1. Picking (C) or (D) amounts to deciding that one of the two inputs quietly wins; nothing in the circuit gives either one priority.

Answer: C) \(Y_1Y_0 = 10\), \(V = 1\)

Handbook: the FE Reference Handbook 10.6 has nothing on encoders. The word encoder does not appear in its 502 pages, and its only occurrence of priority is the IPv6 traffic-class field on p. 404, which is unrelated. The priority-encoder behaviour and the valid bit are knowledge you bring; the input levels and the priority order come from the figure.

Step 1 – Read the figure. \(D_3 = 0\), \(D_2 = 1\), \(D_1 = 1\), \(D_0 = 0\), and the note fixes the order: \(D_3\) highest, \(D_0\) lowest.

Step 2 – Find the highest-priority input that is actually asserted. This is the step the whole item turns on. \(D_3\) ranks highest, but it is at 0, so it is not competing for anything. Working down: \(D_2 = 1\). That is the winner, and \(D_1\) is ignored even though it is also asserted.

Step 3 – Encode its index.

$$2_{10} = 10_2 \qquad\Longrightarrow\qquad Y_1Y_0 = 10$$

Step 4 – The valid bit. \(V\) is the OR of all the inputs:

$$V = D_3 + D_2 + D_1 + D_0 = 0 + 1 + 1 + 0 = 1$$

Its job is to tell \(Y_1Y_0 = 00\) meaning input 0 is asserted apart from \(Y_1Y_0 = 00\) meaning nothing is asserted. Without \(V\) those two situations produce the same code and the encoder is unreadable.

Answer: (C).

The full behaviour, with don't-cares. The lower-priority inputs stop mattering once a higher one is asserted, which is what the \(\times\) entries record:

$$\begin{array}{cccc|ccc} D_3 & D_2 & D_1 & D_0 & Y_1 & Y_0 & V \\ \hline 0 & 0 & 0 & 0 & \times & \times & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & \times & 0 & 1 & 1 \\ 0 & 1 & \times & \times & 1 & 0 & 1 \\ 1 & \times & \times & \times & 1 & 1 & 1 \end{array}$$

The given input, \(0110\), matches the fourth row.

Where the priority actually lives — it is one term. Read the table off as equations and the part is tiny:

$$Y_1 = D_3 + D_2 \qquad Y_0 = D_3 + \overline{D_2}D_1 \qquad V = D_3 + D_2 + D_1 + D_0$$

Now build a plain 4-to-2 encoder instead — the one that just ORs together the codes of whatever is asserted — and it is the same thing with the masking term deleted:

$$Y_1 = D_3 + D_2 \qquad Y_0 = D_3 + D_1$$

The whole of priority is that single \(\overline{D_2}\): it is what stops \(D_1\) from speaking while \(D_2\) is speaking. Substitute this problem's input into both and watch that one term decide the answer:

$$\text{priority: } Y_0 = 0 + \overline{(1)}(1) = 0 \;\Rightarrow\; Y_1Y_0 = 10 \qquad\qquad \text{plain: } Y_0 = 0 + 1 = 1 \;\Rightarrow\; Y_1Y_0 = 11$$

The plain encoder answers 11, a code pointing at \(D_3\) — an input that is not even asserted. That is why a plain encoder is only defined when exactly one input is high, and why the priority version exists.

Step 5 – Eliminate the distractors:

(D) \(11\) with \(V = 1\) is the strongest wrong answer because two different mistakes land on it. It is the plain-encoder output just derived, the ORing failure that the \(\overline{D_2}\) term exists to prevent. It is also what you get by reading \(D_3\) has the highest priority as \(D_3\) wins and encoding 3 without checking whether \(D_3\) is asserted at all. Priority ranks the inputs; it does not assert them.

(A) \(00\) with \(V = 0\) treats two simultaneous highs as an invalid input, which is true of a plain encoder but is exactly what a priority encoder is built to handle — it has a defined output for all sixteen input patterns. And \(V = 0\) specifically claims that no input is asserted, when two of them are.

(B) \(01\) with \(V = 1\) encodes \(D_1\), which would be right if the priority ran the other way, with \(D_0\) highest. Both orderings exist in real parts, so the direction is never assumed — it is read off the device, and here the figure states it.

Answer: B) \(2\)

The maxterm list names the rows where \(F = 0\): the patterns \(ABCD\) = 0000, 0001, 0010, 0100, 0101. Group the zeros on the Handbook's four-variable map as if they were ones. The cells 0, 1, 4, 5 form a block of four in which \(A = 0\) and \(C = 0\) throughout, giving the sum term \((A + C)\); the cells 0 and 2 form a pair with \(A = 0\), \(B = 0\), \(D = 0\), giving \((A + B + D)\). No larger group contains cell 2, since cells 6, 8 and 10 are ones.

$$F = (A + C)(A + B + D)$$

Both terms are essential in the Handbook's sense: the block of four is the only prime implicate covering cells 1, 4 and 5, and the pair is the only one covering cell 2. Two essential prime implicates, and the minimized expression consists of exactly those two. Check cell 2 (0010): \(A + B + D = 0\), so \(F = 0\); and cell 3 (0011), which is a one: \(A + C = 1\) and \(A + B + D = 1\), so \(F = 1\).

1 takes the block of four alone and leaves cell 2 uncovered, so \(F\) would be 1 at 0010 where it must be 0.

3 counts the pair \(\{0, 1\}\) or \(\{0, 4\}\) as a separate term, but those pairs sit inside the block of four and are not prime.

4 treats the zeros as needing one term per pair, ignoring the block of four altogether.

Answer: A) \(D_1 = Q_1 \oplus Q_0\)

Handbook: FE Reference Handbook 10.6, Mathematics → Discrete Math → Finite State Machine, p. 36 (PDF viewer: page 42) — a machine is a finite set of states, a finite set of inputs and a transition function, drawn as a state table or a state diagram. That is where the Handbook stops. It gives no synthesis procedure, and its single use of the word excitation is the synchronous-machine field current on p. 371, not this one.

Step 1 – What is being asked for. For a D flip-flop the input you apply now is the value you want out after the edge, so

$$D_1 = Q_1^{+}$$

and the job is to write the next value of \(Q_1\) as a function of the present \(Q_1\) and \(Q_0\). The timer is what makes the machine step; it is not a data input, so nothing else can appear in the equation.

Step 2 – Turn the diagram into a state table. Follow the four arrows and read each state's assignment out of its circle. The sequence is \(00 \to 01 \to 10 \to 11 \to 00\) — a plain binary up-count.

$$\begin{array}{cc|cc|c} Q_1 & Q_0 & Q_1^{+} & Q_0^{+} & D_1 \\ \hline 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 1 \\ 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 \end{array}$$

Step 3 – Read the \(D_1\) column. It is \(0, 1, 1, 0\): one where the two present-state bits differ, zero where they agree. That is the exclusive-OR.

$$D_1 = Q_1 \oplus Q_0$$

Answer: (A).

Where that comes from, and how it generalises. Derive the partner equation from the same table and the pair reads as arithmetic:

$$D_0 = \overline{Q_0} \qquad\qquad D_1 = Q_1 \oplus Q_0$$

The low bit toggles on every count. The high bit toggles only when the low bit is 1 — and "toggle when a condition holds" is exactly what an exclusive-OR with that condition does, since \(Q \oplus 1 = \overline{Q}\) and \(Q \oplus 0 = Q\). That is the carry rule of binary counting, and it extends without change: bit \(i\) toggles when every bit below it is 1, so

$$D_i = Q_i \oplus (Q_{i-1}Q_{i-2}\cdots Q_0)$$

Step 4 – Eliminate the distractors:

(B) \(\overline{Q_1}\) says the high bit toggles on every count, the way the low bit does. Walk the sequence and it does not: \(Q_1\) is 0, 0, 1, 1 — it changes only every second count, which is what makes it the more significant bit.

(C) \(\overline{Q_0}\) is the excitation equation for the other flip-flop — it is \(D_0\), correct but for the wrong bit. Both columns of the state table are short and neither looks wrong on its own; only the heading tells them apart, so check which column you are reading before simplifying it.

(D) \(Q_1 \odot Q_0\), the exclusive-NOR, is the complement of the answer and it is what \(D_1\) would be if the controller ran backwards, \(00 \to 11 \to 10 \to 01 \to 00\). Trace that sequence and the column comes out \(1, 0, 0, 1\). The arrowheads on the figure are what settle the direction; a ring of four states drawn without them says nothing.